How do I know where to put stitching vias?
I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.
One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.
How do I know how many stitching vias to place and how do I know where to place them?
Here is what the board looks like so far:
Edit:
Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:
pcb-design decoupling-capacitor via ground-plane copper-pour
asked 5 hours ago
D. Patrick
18029
add a comment |
I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.
One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.
How do I know how many stitching vias to place and how do I know where to place them?
Here is what the board looks like so far:
Edit:
Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:
pcb-design decoupling-capacitor via ground-plane copper-pour
asked 5 hours ago
D. Patrick
18029
add a comment |
I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.
One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.
How do I know how many stitching vias to place and how do I know where to place them?
Here is what the board looks like so far:
Edit:
Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:
pcb-design decoupling-capacitor via ground-plane copper-pour
asked 5 hours ago
D. Patrick
18029
I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with 2 supply pins.
One of the recommendations was to add ground pours to the top and bottom layers of the PCB to create low impedance ground connections for the decoupling capacitors and to tie the top and bottom layers with several stitching vias.
How do I know how many stitching vias to place and how do I know where to place them?
Here is what the board looks like so far:
Edit:
Because I'm new to electrical engineering (I'm barely at hobbyist level), it really helps me to see solutions visually. For folks finding this in the future, here's what my latest state is:
pcb-design decoupling-capacitor via ground-plane copper-pour
pcb-design decoupling-capacitor via ground-plane copper-pour
asked 5 hours ago
D. Patrick
18029
asked 5 hours ago
D. Patrick
18029
edited 17 mins ago
asked 5 hours ago
D. Patrick
18029
asked 5 hours ago
D. Patrick
18029
asked 5 hours ago
D. Patrick
18029
18029
add a comment |
add a comment |
2 Answers
2
active
oldest
votes
If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.
But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.
In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.
Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.
If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.
answered 4 hours ago
Edgar Brown
3,485425
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
1
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
add a comment |
Put 4 at each end, and a couple under the body of the cap. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get a Gnd vias between them and C2 and C1.
answered 5 hours ago
CrossRoads
1,1698
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
1
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
add a comment |
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2 Answers
2
active
oldest
votes
2 Answers
2
active
oldest
votes
active
oldest
votes
active
oldest
votes
If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.
But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.
In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.
Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.
If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.
answered 4 hours ago
Edgar Brown
3,485425
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
1
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
add a comment |
If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.
But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.
In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.
Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.
If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.
answered 4 hours ago
Edgar Brown
3,485425
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
1
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
add a comment |
If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.
But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.
In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.
Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.
If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.
answered 4 hours ago
Edgar Brown
3,485425
If you flip C2 and C3 around this could be a 1-layer board. Flipping them, would also reduce parasitic inductances due to the required vias.
But, to answer your question, for your (low-frequency) application, stitching vias serve just one purpose, to reduce the impedance for any current traveling on the planes. That directly implies that areas of the plane that have little or no current, due to being far from the current paths, don’t require any vias.
In your case you only have 4 pads and a pin that conduct current from the plane. You just require vias near those pads and perhaps the pin (vias are much less conductive than the pin itself). Perhaps 4 vias on the capacitors, and 2 near the IC Gnd.
Any additional vias would mostly be cosmetic, it would be hard to tease apart the effects due to reduction in impedance due to the vias from the increase in impedance due to the added holes in the planes.
If this was a high-frequency a application (e.g., >500MHz) vias would be required near the PCB edges, to avoid unintended emissions and you would need to take into account the impedances to the plane underneath signal lines.
answered 4 hours ago
Edgar Brown
3,485425
edited 4 hours ago
answered 4 hours ago
Edgar Brown
3,485425
answered 4 hours ago
Edgar Brown
3,485425
answered 4 hours ago
Edgar Brown
3,485425
3,485425
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
1
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
add a comment |
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
1
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
If I flip the caps, the Vss trace will still be short enough? And the ground pour on top will be low enough inductance that I don’t need the pour on bottom at all?
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
I meant Vdd trace won’t be too long.
– D. Patrick
3 hours ago
1
1
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
@D.Patrick If you flip C2 and C3 VddI2C could actually become shorter. If you are doing a double-layer board (the difference in price might be negligible) put the plane anyway. It does not hurt anything and it will provide better shielding, a negligible effect given the application, but better anyway.
– Edgar Brown
2 hours ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
I added an image to the end of my question that shows my attempt to implement your suggestions. Did I more or less capture what you had in mind? (I also moved a few things around because I wanted to label a some of the pins, but I don't think I changed the circuit substantially). Thanks again for your help!!
– D. Patrick
14 mins ago
add a comment |
Put 4 at each end, and a couple under the body of the cap. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get a Gnd vias between them and C2 and C1.
answered 5 hours ago
CrossRoads
1,1698
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
1
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
add a comment |
Put 4 at each end, and a couple under the body of the cap. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get a Gnd vias between them and C2 and C1.
answered 5 hours ago
CrossRoads
1,1698
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
1
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
add a comment |
Put 4 at each end, and a couple under the body of the cap. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get a Gnd vias between them and C2 and C1.
answered 5 hours ago
CrossRoads
1,1698
Put 4 at each end, and a couple under the body of the cap. I don't know that there is an exact science behind it. I try to get Gnd vias near the Gnd end of the caps too. You could move C3 & C4 up a little to get a Gnd vias between them and C2 and C1.
answered 5 hours ago
CrossRoads
1,1698
answered 5 hours ago
CrossRoads
1,1698
answered 5 hours ago
CrossRoads
1,1698
answered 5 hours ago
CrossRoads
1,1698
1,1698
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
1
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
add a comment |
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
1
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
Thanks! Why put one under the body of the caps?
– D. Patrick
5 hours ago
1
1
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
Sorry, that was supposed to be 'chip'.
– CrossRoads
3 hours ago
add a comment |
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